`timescale 1ns/1ps
module circuit4_top ;
    reg clk,reset,load;
    reg [3:0]Data_in;
    wire [3:0] Data_out;

    always # 1 clk = ~clk;
    initial begin
        clk = 0;
        reset = 0;
        Data_in = 0;
        load = 0;
        # 1 reset = 1 ;
        # 3 reset = 0 ;
        # 2 load =1;
        # 1 Data_in =4'b1111;
        # 2 Data_in =4'b1010;
        # 1 load =0;
        # 1 Data_in= 4'b1110;
        # 2 reset = 1;
        # 2 $finish;
    end
    circuit4 c4(Data_out,Data_in,load,clk,reset);
	initial
	begin
    	$dumpfile("test.vcd");
    	$dumpvars(0, c4);
 	end
endmodule

module circuit4(Data_out,Data_in,load,clock,reset);
	input clock,reset,load;
    input [3:0] Data_in;
    output reg [3:0] Data_out;
    wire [3:0] D_temp;
    assign D_temp = load?Data_in:Data_out;
    always @(posedge clock)
        if(reset)
            Data_out <= 4'b0;
    	else
            Data_out <= D_temp;
endmodule
